DVCon 2003 Design and Verification Conference & Exhibition February 24-26, 2003 DoubleTree Hotel San Jose San Jose, CA 95110 http://www.dvcon.org DVCon 2003 is the premier conference on the usage of Hardware Description Languages (HDLs), and Hardware Verification Languages (HVLs) for the design and verification of electronic systems and integrated circuits. CONFERENCE HIGHLIGHTS * 38 Papers presented, 7 Tutorials * Monday Luncheon Keynote, Aart de Geus, Chairman & CEO of Synopsys: Design for Verification: A New Paradigm * Tuesday Luncheon & Presentations: Updates on the SystemC Standard Organizers: Stan Kirolikoski, Chairman, OSCI Kevin Kranen, President, OSCI COMPLIMENTARY MONDAY PANEL SESSIONS: Panel 1: Is Methodology Driving Language, or Vice Versa? Moderator: Gabe Moretti, EDN Panelists: Dennis Brophy, Model Technology, a Mentor Graphics Co. Manoj Ghandi, Synopsys, Inc. Faisal Hague, Cisco, Inc. Stan Krolikoski, Cadence Design Systems, Inc. Shrenik Mehta, Sun Microsystems Panel 2: Verilog and Assertions - Do they Mix? Moderator: Clifford E. Cummings, Sunburst Design, Inc. Panelists: Dennis Brophy, Model Technology a Mentor Graphics Co. Harry Foster, Verplex Systems Inc. Erich Marschner, Cadence Design Systems, Inc. Mike McNamara, Verisity Design, Inc. Stephen Meier, Synopsys, Inc. Panel 3: EDA Directions Moderator: John Cooley, ESNUG Panelists: Bernard Aronson, Synplicity, Inc. Jacques Benkoski, Monterey Design Systems Erach Desai, American Technology Research David Evans, Forte Design Systems Moshe Gavrielov, Versity Design, Inc. Lucio Lanza, Lanza Tech Ventures Rajeev Madhavan, Magma Design Automation, Inc. For a complete agenda, visit: http://www.dvcon.org/techprog.html CONFERENCE REGISTRATION REGISTRATION CLOSES: TUESDAY, FEBRUARY 11TH! The advance registraiton rate is now available until Tuesday, February 11th! Register now to save $25! You may register on-line, via mail or fax. Full conference registration includes admission to all technical sessions on Monday and Tuesday, the Monday evening cocktail reception, daily coffee service, lunch and a copy of the CD-ROM proceedings. HOTEL RESERVATIONS SUNDAY, FEBRUARY 9TH DEADLINE FOR $149 RATE! The DVCon discounted room rate of $149 single/double is limited, and we encourage you to make your reservations as soon as possible. Reservations may be made by contacting the hotel directly at 408-453-4000. TUTORIALS, WEDNESDAY, FEBRUARY 26, 2003 Tutorial 1: Practical Verilog for Chip-level Verification Tutorial 2: Functional Verification with Specman Elite, Step-by-Step Tutorial 3: Finding More Bugs with VERA's Constraint-Driven Stimulus Generation Tutorial 4: The Sugar 2.0 Property Specification Language - A Language for All Seasons Tutorial 5: Transaction-based Modeling and Verification with SystemC Tutorial 6: An Introduction to Smart Verification Using SystemVerilog Tutorial 7: The Design Flow - Linking Design, Verification, and Common Sense to Build Chips that Work VISIT EXHIBITS AND PLAY WHO WANTS TO BE MULTI-MILLION GATE DESIGNER! Exhibits are open to the public on both conference days. Join us for some interactive fun after the panel sessions and play the EDA version of "Who wants to be a Multi-Million Gate Designer" by gathering gates to win prizes and a chance to sit in the squared circle with the Accellera Chairman Dennis Brophy. Exhibit Hours: Monday, February 24th: 12pm-7pm Tuesday, February 25th: 9am-12pm We look forward to seeing you at DVCon 2003, February 24-26, 2003 at the DoubleTree Hotel San Jose. ********************************************************************** This is the list for the Accellera Member Announcements. You have been subscribed to this list if you have either requested Accellera membership or attended a Accellera sponsored conference. This list is used to send periodic announcements on upcoming events and other useful information. If you would like to remove yourself from this list, please click: http://mpassociates.post.intellimedia.com/UM/U.asp?B1031.12346.134.10274 and you will be removed immediately! Thank you!